The present invention relates to DRAM circuits and, more specifically to a circuit and method for maintaining a desired read latency in a high speed DRAM.
A typical DRAM memory system has an external DRAM controller that makes read and write requests to a DRAM memory device. When making a read request the controller expects data within the memory device to be available on a data bus within a predetermined read latency, which is usually a predetermined number of system clock cycles, which are external to the DRAM device, after a read request is made by the controller e.g., eight external clock cycles.
The problems with maintaining read data latency in high speed DRAM arise from the necessity to align data with the external clock using an internal delay locked loop (DLL), which generates timing signals, including a read clock signal, for internal DRAM operations. The phase relationship between the external DRAM clock, an internal command/address capture clock and the DLL output clock, which is used to generate the read clock signal, is completely arbitrary and dependent on frequency and process, voltage, and temperature (PVT) variations. The command capture clock is delayed relative to the external clock by the clock receiver and other clock distribution delays. The DLL is back timed relative to the external clock by the delay of the data output circuits, but receives its input from an internal clock receiver and also has adjustments made to its output signals that are not synchronized with the external clock. A difference in phase near or greater than a complete clock cycle creates difficulty in controlling timing between the command/address capture clock domain and the DLL clock domain.
As noted, internally, the DRAM memory device has its own DLL driven clock system that receives the external clock signal and develops from the external clock several different internal clock signals, including a read clock signal, for internal operation of the memory device. The internal clock system of a known high speed memory device produces at least two clock domains. The first clock domain represents the timing used in the bulk of the logic circuits and to drive the memory array core. The timing for the first domain is produced from the internal clock receiver, which is buffered from the external free running system clock. The phase of the clock signal in the first domain relative to the external clock is dependent upon delays in the clock receiver that receives the external clock signal. The second domain, also derived from the external system clock, represents the timing of a back-timed read clock signal. This clock domain is produced by the delay lock loop DLL and associated clock trees. This second clock domain produces a read clock, for operating data read latches. The read clock is provided to the read latch with a desired phase relationship to the external system clock. The second clock domain compensates for delays in the data output path in order to produce a read clock signal that operates the output data latches to achieve a specified phase alignment with the external system clock.
Neither of these two clock domains truly accurately reflects the timing of the external system clock, particularly at high frequencies of operation and the timing of the clock signals in the two domains may criss-cross one another during memory device operation due to process, voltage and temperature (PVT) variations. Consequently, a problem may arise in that one clock domain responsible for delivery of read data to an output latch may cause this data to be delivered at a different time from when the back-timed read clock for latching that data is present at the latch, or when the data is actually required to be driven to an external bus.
In order to meet a specified read latency the memory device must be able to count clock signals following receipt of a READ command and activate the output latch and data driver to latch output data with the back-timed read clock and drive the bus at the precise time necessary to produce the specified read latency.
Since the amount of read clock back-timing becomes indeterminate during high speed operation relative to the data availability, it is very difficult to control the read clock and guarantee a correct data output and a specific read latency as measured in external clock cycles.
The present invention provides a method and apparatus compensating for uncertainty and variations in the amount of read clock back timing relative to data flow in order to maintain a specified read latency. The present invention is a DRAM circuit that utilizes the DLL loop delay as a reference in order to maintain a specified read latency. The loop delay of the DLL represents the number of clock cycles it takes for a clock edge to travel from the reference input of the phase detector of the DLL to the feedback input of the phase detector. Under ideal conditions, the phase difference between the two clock signals is 0 degrees. As a result, the delay component of the DLL can be used to maintain a specified read latency for a high speed DRAM.
In addition, the present invention utilizes a slave delay line to the primary DLL line in order to track adjustments made to the primary delay line used for DLL output clock adjustments. The slave delay line can be used to transfer a signal that is synchronized to the DLL input clock domain so the signal arrives at the output of the slave delay line synchronized to the DLL output clock domain thereby experiencing the same delay. Consequently, the delayed signal is subject to the same PVT or other timing variations that is experienced by the primary DLL line and is back-timed for output path delays by the same amount as the DLL primary signal.
In the present invention, a reset signal is generated at DRAM initialization and starts an upstream counter, which counts external clock cycles, and is also passed through the slave delay line to start a downstream counter which counts clock signals corresponding to the read clock signals provided by the DLL and associated clock tree. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the DLL to produce an internal read clock signal.
In one embodiment, when a READ command is received from an external controller, the contents of the upstream counter are loaded into a FIFO/Adder. This count value is altered by either adding or subtracting the internal read latency value IRLVAL, a value generated by a latency offset calculator, calculating the internal read latency of the DRAM circuit from various parameters. The sum of IRLVAL with the value of the upstream counter produces a compensated count value, CCVAL. The compensated count value is compared with the count value produced by the downstream counter in a comparator.
Once the downstream count has a count value equivalent to the compensated count value, the comparator passes a signal to a line driver enable counter, which in turn passes an output signal to the output circuit to cause read data to be placed on an output line latched into an output latch by a read clock generated by the DLL with a specified read latency. In burst mode, the line driver enable counter passes multiple output signals to the output circuit for each data signal of a burst.
Thus, even if the back-timing of the read clock output varies, the output data is placed on the output line in synchronism with the external read clock.
In a second embodiment, the internal read latency value is used to offset the count value of the downstream counter instead of the upstream counter.
The foregoing and other features of the invention will become more apparent from the detailed description of the exemplary embodiments of the invention given below in connection with the accompanying drawings.